charlesmarsh.dev

EngineerUndergrad · 2023

Pipelined RISC-V Processor

A 32-bit, five-stage pipelined RISC-V CPU with a branch predictor, written in SystemVerilog and running on an FPGA.

Block diagram of the five-stage pipelined OTTER processor.

This processor was the final project of Cal Poly’s three-course computer design sequence. Over the sequence I went from logic gates to a working CPU: a 32-bit RISC-V core (the “OTTER”) with a five-stage pipeline and a branch predictor, synthesized onto a Xilinx FPGA.

What it took

  • Digital design. Building the datapath from basic logic, with control written as finite-state machines.
  • Architecture. Pipelining, and the data and control hazards it creates: forwarding, stalls, and branch prediction to keep the pipeline full.
  • Verification. Simulating and testing every component in SystemVerilog before it ever touched hardware.
  • Software. Writing and debugging RISC-V assembly, and C benchmarks (matrix multiply and add) to measure the finished core.

Simulation waveform. Simulation waveform used to verify the pipeline’s timing.

FPGA power report. Power report for the design on the FPGA.